1. Field of the Invention
This invention relates to integrated circuits, and more particularly, to the arrangement of memory and associated access paths within an integrated circuit.
2. Description of the Related Art
Computers and other types of electronic systems often include a memory hierarchy having several different layers. Among these layers may be included non-volatile storage (e.g., hard disk storage), random access memory (RAM), and one or more levels of cache memory. Processor-based systems may include a processor having one or more cores, wherein each of the one or more cores includes one or more cache memories. For example, many processors include at least one processor core having an instruction cache and a data cache, which may be at the top of the memory hierarchy. A cache memory at the top of the memory hierarchy may be referred to as a level one (or L1) cache. Many processors also include a level two (or L2) cache, which may be shared by the data and instruction caches of a processor core, and furthermore, may be shared by multiple processor cores in multi-core processors.
When provided on an integrated circuit (IC), some of these types of memories, such as L2 caches, may be organized into what are known as memory supercells. A memory supercell is a 2-dimensionally array of memory banks (e.g., rows and columns of memory banks) that shares a common interface (sometimes referred to as a ‘tap point’). In particular, when designing an IC, each memory bank may be in the form of a cell whose location on the IC die and interconnects to other defined cells and/or other functional units may be manipulated by an IC design tool. A memory supercell is simply a collection of such memory bank cells interconnected to form a larger, unified memory cell that may similarly be located on the IC by the design tool.
In such a memory supercell, a given address maps to one bank of the supercell. Information transferred to a supercell during a write operation may be received by the interface and then routed to a location in a memory bank indicated by the address which maps thereto. Similarly, when performing a read operation, information may be routed from an addressed location in one of the memory banks of the supercell to the interface, and thus to the requesting device.